Eliminating_hazards Hazard_(computer_architecture)

1 eliminating hazards

1.1 generic

1.1.1 pipeline bubbling


1.2 data hazards

1.2.1 operand forwarding
1.2.2 examples


1.3 control hazards (branch hazards)
1.4 other techniques

eliminating hazards
generic
pipeline bubbling

bubbling pipeline, termed pipeline break or pipeline stall, method preclude data, structural, , branch hazards. instructions fetched, control logic determines whether hazard could/will occur. if true, control logic inserts no operations (nops) pipeline. thus, before next instruction (which cause hazard) executes, prior 1 have had sufficient time finish , prevent hazard. if number of nops equals number of stages in pipeline, processor has been cleared of instructions , can proceed free hazards. forms of stalling introduce delay before processor can resume execution.

flushing pipeline occurs when branch instruction jumps new memory location, invalidating prior stages in pipeline. these prior stages cleared, allowing pipeline continue @ new instruction indicated branch.

data hazards

there several main solutions , algorithms used resolve data hazards:

insert pipeline bubble whenever read after write (raw) dependency encountered, guaranteed increase latency, or
use out-of-order execution potentially prevent need pipeline bubbles
use operand forwarding use data later stages in pipeline

in case of out-of-order execution, algorithm used can be:

scoreboarding, in case pipeline bubble needed when there no functional unit available
the tomasulo algorithm, uses register renaming, allowing continual issuing of instructions

the task of removing data dependencies can delegated compiler, can fill in appropriate number of nop instructions between dependent instructions ensure correct operation, or re-order instructions possible.

operand forwarding

examples

in following examples, computed values in bold, while register numbers not.

for example, write value 3 register 1, (which contains 6), , add 7 register 1 , store result in register 2, i.e.:

instruction 0: register 1 = 6
instruction 1: register 1 = 3
instruction 2: register 2 = register 1 + 7 = 10

following execution, register 2 should contain value 10. however, if instruction 1 (write 3 register 1) not exit pipeline before instruction 2 starts executing, means register 1 not contain value 3 when instruction 2 performs addition. in such event, instruction 2 adds 7 old value of register 1 (6), , register 2 contains 13 instead, i.e.:

instruction 0: register 1 = 6
instruction 2: register 2 = register 1 + 7 = 13
instruction 1: register 1 = 3

this error occurs because instruction 2 reads register 1 before instruction 1 has committed/stored result of write operation register 1. when instruction 2 reading contents of register 1, register 1 still contains 6, not 3.

forwarding (described below) helps correct such errors depending on fact output of instruction 1 (which 3) can used subsequent instructions before value 3 committed to/stored in register 1.

forwarding applied example means there no wait commit/store output of instruction 1 in register 1 (in example, output 3) before making output available subsequent instruction (in case, instruction 2). effect instruction 2 uses correct (the more recent) value of register 1: commit/store made , not pipelined.

with forwarding enabled, instruction decode/execution (id/ex) stage of pipeline has 2 inputs: value read register specified (in example, value 6 register 1), , new value of register 1 (in example, value 3) sent next stage instruction execute/memory access (ex/mem). added control logic used determine input use.

control hazards (branch hazards)

to avoid control hazards microarchitectures can:

insert pipeline bubble (discussed above), guaranteed increase latency, or
use branch prediction , make educated guesses instructions insert, in case pipeline bubble needed in case of incorrect prediction

in event branch causes pipeline bubble after incorrect instructions have entered pipeline, care must taken prevent of wrongly-loaded instructions having effect on processor state excluding energy wasted processing them before discovered loaded incorrectly.

other techniques

memory latency factor designers must attend to, because delay reduce performance. different types of memory have different accessing time memory. thus, choosing suitable type of memory, designers can improve performance of pipelined data path.