Types Hazard_(computer_architecture)

1 types

1.1 data hazards

1.1.1 read after write (raw)

1.1.1.1 example


1.1.2 write after read (war)

1.1.2.1 example


1.1.3 write after write (waw)

1.1.3.1 example




1.2 structural hazards
1.3 control hazards (branch hazards)

types
data hazards

data hazards occur when instructions exhibit data dependence modify data in different stages of pipeline. ignoring potential data hazards can result in race conditions (also termed race hazards). there 3 situations in data hazard can occur:

consider 2 instructions i1 , i2, i1 occurring before i2 in program order.

read after write (raw)

(i2 tries read source before i1 writes it) read after write (raw) data hazard refers situation instruction refers result has not yet been calculated or retrieved. can occur because though instruction executed after prior instruction, prior instruction has been processed partly through pipeline.

example

for example:

i1. r2 <- r1 + r3

i2. r4 <- r2 + r3

the first instruction calculating value saved in register r2, , second going use value compute result register r4. however, in pipeline, when operands fetched 2nd operation, results first not yet have been saved, , hence data dependency occurs.

a data dependency occurs instruction i2, dependent on completion of instruction i1.

write after read (war)

(i2 tries write destination before read i1) write after read (war) data hazard represents problem concurrent execution.

example

for example:

i1. r4 <- r1 + r5

i2. r5 <- r1 + r2

in situation chance i2 may finish before i1 (i.e., concurrent execution), must ensured result of register r5 not stored before i1 has had chance fetch operands.

write after write (waw)

(i2 tries write operand before written i1) write after write (waw) data hazard may occur in concurrent execution environment.

example

for example:

i1. r2 <- r4 + r7

i2. r2 <- r1 + r3

the write (wb) of i2 must delayed until i1 finishes executing.

structural hazards

a structural hazard occurs when part of processor s hardware needed 2 or more instructions @ same time. canonical example single memory unit accessed both in fetch stage instruction retrieved memory, , memory stage data written and/or read memory. can resolved separating component orthogonal units (such separate caches) or bubbling pipeline.

control hazards (branch hazards)

branching hazards (also termed control hazards) occur branches. on many instruction pipeline microarchitectures, processor not know outcome of branch when needs insert new instruction pipeline (normally fetch stage).