Generic Hazard_(computer_architecture)

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bubbling pipeline, termed pipeline break or pipeline stall, method preclude data, structural, , branch hazards. instructions fetched, control logic determines whether hazard could/will occur. if true, control logic inserts no operations (nops) pipeline. thus, before next instruction (which cause hazard) executes, prior 1 have had sufficient time finish , prevent hazard. if number of nops equals number of stages in pipeline, processor has been cleared of instructions , can proceed free hazards. forms of stalling introduce delay before processor can resume execution.


flushing pipeline occurs when branch instruction jumps new memory location, invalidating prior stages in pipeline. these prior stages cleared, allowing pipeline continue @ new instruction indicated branch.








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