Implementation_concepts Tomasulo_algorithm

1 implementation concepts

1.1 common data bus
1.2 instruction order
1.3 register renaming
1.4 exceptions

implementation concepts

tomasulo s floating point unit

the following concepts necessary implementation of tomasulo s algorithm:

common data bus

the common data bus (cdb) connects reservation stations directly functional units. according tomasulo preserves precedence while encouraging concurrency . has 2 important effects:

instruction order

instructions issued sequentially effects of sequence of instructions, such exceptions raised these instructions, occur in same order on in-order processor, regardless of fact being executed out-of-order (i.e. non-sequentially).

register renaming

tomasulo s algorithm uses register renaming correctly perform out-of-order execution. general-purpose , reservation station registers hold either real value or placeholder value. if real value unavailable destination register during issue stage, placeholder value used. placeholder value tag indicating reservation station produce real value. when unit finishes , broadcasts result on cdb, placeholder replaced real value.

each functional unit has single reservation station. reservation stations hold information needed execute single instruction, including operation , operands. functional unit begins processing when free , when source operands needed instruction real.

exceptions

practically speaking, there may exceptions not enough status information exception available, in case processor may raise special exception, called imprecise exception. imprecise exceptions cannot occur in non-oooe implementations, processor state changed in program order (see risc pipeline exceptions).

programs experience precise exceptions, specific instruction took exception can determined, can restart or re-execute @ point of exception. however, experience imprecise exceptions cannot restart or re-execute, system cannot determine specific instruction took exception.