Data_hazards_2 Hazard_(computer_architecture)

examples

in following examples, computed values in bold, while register numbers not.

for example, write value 3 register 1, (which contains 6), , add 7 register 1 , store result in register 2, i.e.:

instruction 0: register 1 = 6
instruction 1: register 1 = 3
instruction 2: register 2 = register 1 + 7 = 10

following execution, register 2 should contain value 10. however, if instruction 1 (write 3 register 1) not exit pipeline before instruction 2 starts executing, means register 1 not contain value 3 when instruction 2 performs addition. in such event, instruction 2 adds 7 old value of register 1 (6), , register 2 contains 13 instead, i.e.:

instruction 0: register 1 = 6
instruction 2: register 2 = register 1 + 7 = 13
instruction 1: register 1 = 3

this error occurs because instruction 2 reads register 1 before instruction 1 has committed/stored result of write operation register 1. when instruction 2 reading contents of register 1, register 1 still contains 6, not 3.

forwarding (described below) helps correct such errors depending on fact output of instruction 1 (which 3) can used subsequent instructions before value 3 committed to/stored in register 1.

forwarding applied example means there no wait commit/store output of instruction 1 in register 1 (in example, output 3) before making output available subsequent instruction (in case, instruction 2). effect instruction 2 uses correct (the more recent) value of register 1: commit/store made , not pipelined.

with forwarding enabled, instruction decode/execution (id/ex) stage of pipeline has 2 inputs: value read register specified (in example, value 6 register 1), , new value of register 1 (in example, value 3) sent next stage instruction execute/memory access (ex/mem). added control logic used determine input use.